INTRODUCTION TO MICROFABRICATION JAEGER PDF

Field Effect Devices Robert F. Dispatched from the UK in 10 business days When will my order arrive? Introduction to Microelectronic Fabrication : Richard C. Jaeger : Trivia About Introduction to M Mohit marked it as to-read Jul 15, Jaeger, is a concise survey of the most up-to-date techniques in the field.

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You are on page 1of Search inside document V2O7L. Jaeger—2nd Edition pom. Modular series on solid state devices;. Integrated circuits —Very large scale integration—Design and construction —Congresses. II, Series. These efforts include the development, research, and testing of the theories and programs to determine their effectiveness. The author and publisher make no warranty of any kind, expressed or implied, with regard to these pro- 1 the documentation contained in this book.

The author and publisher shall not be liable in any event for incidental or consequential damages in connection with, or arising out of, the furnishing, performance, or grams 0 use of these programs. Pearson Education North Asia Ltd. Factors Influencing Oxidation Rate 46 3. The Diffusion Coefficient 72 4.

Basic Multilevel Metallization 7. More-Aggressive Design Rules 9. Transit Time Additionally, the pervasive use of integrated circuits requires a broad range of engineers in the electronics and allied industries to have a basic under- standing of the behavior and limitations of ICs.

One of the goals of this book is to address the educational needs of individuals with a wide range of backgrounds. This text presents an introduction to the basic processes common to most IC technologies and provides a base for understanding more advanced processing and design courses.

Chapter 1 provides an overview of IC processes, and Chapters then focus on the basic steps used in fabrication, including lithography, oxidation, diffusion, ion implantation and thin film deposition, and etching, Interconnection technology, packag- ing, and yield are covered in Chapters 7 and 8.

Itis important to understand interactions between process design, device design, and device layout. For this reason, Chapter 9 and 10 on MOS and bipolar process integration have been included. Major changes in the second edition of this text include new or expanded cover- age of lithography and exposure systems, trench isolation, chemical mechanical polish- ing, shallow junctions, transient-enhanced diffusion, copper Damescene processes, and process simulation.

The problem sets have been expanded, and additional information on measurement techniques has been included. The text evolved from notes originally developed for a course introducing seniors and beginning graduate students to the fabrication of solid-state devices and integrated circuits.

A basic knowledge of the material properties of silicon is needed. An introductory knowledge of electronic components such as resistors, diodes, and MOS and bipolar transistors is also useful The material in the book is designed to be covered in one semester. In our case, the microelectronics fabrication course is accompanied by a corequisite laboratory. Design, fabrication, and testing are completed within the semester. Students from a variety of disciplines, including electrical, mechanical, chemical, and materials engineering; com- puter science; and physics, are routinely enrolled in the fabrication classes.

Hamilton and W. Howard, Integrated Circuit Engineering by A. Glaser and G. Runyon and K. Campbell Thanks also go to the many colleagues who have provided suggestions and encouragement for the new edition and especially to our laboratory manager Charles Ellis who has been instrumental in molding the laboratory sections of our course.

Silicon is the dominant material used through- out the IC industry today, and in order to conserve space, only silicon processing will be discussed in this book. However, all of the basic processes discussed here are applic- able to the fabrication of compound semiconductor integrated circuits ICs such aS gallium arsenide or indium phosphide, as weil as thick- and thin-film hybrid ICs. Germanium was one of the first materials to receive wide attention for use in semiconductor device fabrication, but it was rapidly replaced by silicon during the early s.

Silicon emerged as the dominant material, because it was found to have two major processing advantages. Silicon can easily be oxidized to form a high-quality electrical insulator, and this oxide layer also provides an excellent barrier layer for the selective diffusion steps needed in integrated-circuit fabrication.

Silicon was also shown to have a number of ancillary advantages. It is a very abundant element in nature, providing the possibility of a low-cost starting material. It has a wider bandgap than germanium and can therefore operate at higher tempera- tures than germanium.

In retrospect, it appears that the processing advantages were the dominant reasons for the emergence of silicon over other semiconductor materials. The first successful fabrication techniques produced single transistors on a rec tangular silicon die mm on a side. The first integrated circuits, fabricated at Texas Instruments and Fairchild Semiconductor in the early s, included several transis- tors and resistors to make simple logic gates and amplifier circuits.

From this modest beginning, the level of integration has been doubling every one to two years, and we have now reached integration levels of billions of components on a mm x mm die [].

One-giga- bit RAMs are currently being produced with photographic features measuring between 0,13 and 0. MOS transistors with dimensions below 0. Many wafers are processed at the same time, and the same silicon chip is replicated as many times as possible on a wafer of a given size.

The size of sili- con wafers has steadily increased from 1-,2-,3-, 4-, 5-, and 6-in. See Fig. Wafers with mm diameters will be in full production in the near future, and mm wafers are pro- jected to be in used by the end of the decade. Wafer thicknesses range from approximately to microns. Large-diameter wafers must be thicker in order to maintain structural integrity and planarity during the wide range of processing steps encountered during IC fabrication.

Figure 1. For a given wafer processing cost, the more dice per wafer, the lower the individual die cost becomes. Thus, there are strong economic forces driving the IC industry to continually move to larger and larger wafer sizes.

The complexities of memory chips and microprocessors have both grown exponentially with time. In the three decades since , memory density has grown by a factor of more than 10 million from the bit chip to the 1-Gb memory chip, as indicated in Fig. Similarly, the number of transistors on a microproces- sor chip has increased by a factor of more than five thousand since Fig 1. Since the commercial introduction of the integrated circuit, these increases in density have been achieved through a continued reduction in the minimum line width, or minimum feature size, that can be defined on the surface of the integrated circuit, as shown in Fig.

These trends and future projections are summarized in Table 1. The ITRS is updated every three years; the projections are mind-boggling, even for those of us who have worked in the industry for many years. By the year , MOS transistor gate lengths are pro- jected to reach 30 nm 0. It remains to be seen whether the industry meets these projections.

However, progress will be impressive, even if only a fraction of the projections are achieved. Today, most of the dimensions are specified using the metric system, although Imperial units are occasionally still used. The n-channel MOS transistor is formed in a p-type substrate. Thin and thick silicon-dioxide regions on the surface form the gate insulator of the transistor and serve to isolate one device from another.

A thin film of polysilicon is used to form the gate of the transistor, and a metal such as aluminum is used to make contact to the source and drain, Interconnections between devices can be made using the diffusions and the layers of polysilicon and metal. Silicon dioxide is again used as an insulator, and aluminum is used to make electrical contact to the emitter, base, and collector of the transistor.

This process is called oxidation. Metal films can be deposited through evaporation by heating the metal to its melting point in a vacuum. Thin films of silicon nitride, silicon dioxide, polysilicon, and metals can all be formed through a process known as chemical vapor deposition CVD , in which the material is deposited out of a gaseous mixture onto the surface of the wafer.

Metals and insulators may also be deposited by a process called sputtering. In order to build devices and circuits, the n- and p-type regions must be formed selectively in the surface of the wafer. Silicon dioxide, silicon nitride, polysilicon, photo resist, and other materials can all be used to mask areas of the wafer surface to prevent 6 Chapter 1 An Overview of Microelectronic Fabrication 10! Window patterns are trans- ferred to the wafer surface from a mask through the use of optical techniques.

The masks are also produced using photographic reduction techniques. Photolithography includes the overall process of mask fabrication, as well as the process of transferring patterns from the masks to the surface of the wafer.

The starting wafer is first oxidized to form a thin- pad oxide layer of silicon dioxide SiO, that protects the silicon surface. Mask 1 defines the active transistor areas. A boron implantation is per- formed and followed by an oxidation step. The nitride serves as both an implantation mask and an oxidation mask. After the nitride and thin oxide padding layers are removed, a new thin layer of oxide is grown to serve as the gate oxide for the MOS transistors. Following gate-oxide growth, a boron implantation is commonly used to adjust the threshold voltage to the desired value.

Polysilicon is deposited over the complete wafer using a CVD process. The sec- ond mask defines the polysilicon gate region of the transistor.

Polysilicon is etched away everywhere except over the gate regions and the areas used for interconnection. The implanted impurity may be driven in deeper with a high-temperature diffusion step. More oxide is deposited on the surface, and contact openings are defined by the third mask step. A passivation layer of phosphosilicate glass or silicon nitride not shown in Fig. Wafers with diameters of 1, 1.

The silicon wafers are identified by a standard system! These flats are ground into the silicon ingot before it is sliced into wafers and are used to indicate the wafer type n-type or p-type and the surface orientation or.

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INTRODUCTION TO MICROELECTRONIC FABRICATION BY RICHARD C.JAEGER PDF

Cressler Book Resume: We are in the center of the most life-changing technological revolution the Earth has ever known. In little more than 65 years, an eye-blink in human history, a single technological invention has launched the proverbial thousand ships, producing the most sweeping and pervasive set of changes ever to wash over humankind; changes that are reshaping the very core of human existence, on a global scale, at a relentlessly accelerating pace. And we are just at the very beginning. Silicon Earth: Introduction to Microelectronics and Nanotechnology introduces readers with little or no technical background to the marvels of microelectronics and nanotechnology, using straightforward language, an intuitive approach, minimal math, and lots of pictures. The general scientific and engineering underpinnings of microelectronics and nanotechnology are described, as well as how this new technological revolution is transforming a broad array of interdisciplinary fields, and civilization as a whole.

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Introduction.to.Microelectronic.fabrication R.C.jaeger

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